This year Open Source Hardware Camp will take place over the weekend
of Saturday 2nd & Sunday 3rd September, hosted as part of the Wuthering
Bytes festival in Hebden Bridge, which in 2017 will take place over the
course of 10 days (again!)
We will be returning to the Birchcliffe Centre in Hebden Bridge, which
benefits from the convenience of adjoining, budget accommodation.
Proposals for talks and workshops for OSHCamp 2017 are invited!
There is no theme and topics may include, for example:
* Open source hardware projects
* Open development practices and principles
* Novel/interesting/fun projects built using open source hardware
* Tools (hardware and software)
* Skills and techniques, e.g. PCB fab, DIY SMT assembly
* Relevant technologies, e.g. SPI/I2C bus programming
* ...something else relevant to the community
If you would like to give a talk on the Saturday and/or run a workshop
on the Sunday please contact me off-list.
**** Note that the deadline for submitting titles and abstracts is
Monday 1st May. If you would like to discuss ideas etc. please get in
touch sooner, rather than later. ****
Other events running as part of Wuthering Bytes 2017 and which may be of
* Fri 1st: Wuthering Bytes Festival Day
* Wed 6th & Thurs 7th: Chip Hack (http://chiphack.org/)
* Thurs 7th PM & Fri 8th AM: EDSAC Challenge
* Fri 8th AM - Sunday 10th PM: GNU ORConf (http://orconf.org/)
Further details on these events to be provided in due course.
PS. If you are planning on coming along and thinking of staying at the
adjoining hosted, it is worth noting that this can book up quickly.
PPS. Super Early Bird tickets for the super organised:
(pretty sure Eventbrite don't take payment until after the event).
We welcome you to join us at the University of Cambridge on April 20-21,
2017 for the NetFPGA Developers Summit .
Held immediately prior to Eurosys 2017, this event is intended to permit
participants attend both events with reduced intercontinental travel.
The programme includes presentations, live demonstrations, and group
discussions on topics that are of an interest to the NetFPGA community.
This event will run "un-conference style" in that we brainstorm the actual
session schedule on the first morning, with a focus on interactive topics
that reflect the interests and exploit the knowledge of the attendees --
but there's also room for traditional talks, etc. There are plenty of
break-out rooms for small groups to meet as they see fit.
Confirmed topics include:
* Running P4 programmes on NetFPGA
* Low latency networking
* Running network services in hardware
* Optical networks
* Traffic control tools
* More -- See the draft programme on the Wiki 
See you in Cambridge,
The NetFPGA Team
The ORCONF 2017 CFP is out! Why not head up to Hebden Bridge and make a
week of it, with Open Source Hardware Camp, ORCONF and Chip Hack :o)
-------- Forwarded Message --------
Subject: [Orconf-announce] ORConf 2017 call for participation
Date: Wed, 15 Mar 2017 23:03:14 +1100
From: Julius Baxter <julius(a)fossi-foundation.org>
ORConf 2017 will be held in Hebden Bridge in the UK from Friday to
Sunday, September 8th to the 10th.
I'd like to announce that we've opened submissions for presentations,
posters and hardware displays at the event. Proposals may be submitted
through this form:
ORConf aims to be an event aimed at anyone involved in free and open
source computer system design, with an emphasis on open source digital
design. So if you contribute to a tool to help put systems together, or
develop on and debug them, or publish components and IP, or even make
fully-open source chips(!) we'd very much like to hear from you!
ORConf this year is being held as part of the esteemed Wuthering Bytes
Festival of Technology: http://wutheringbytes.com/ There will be events
in Hebden Bridge starting September 1st, so do check it out.
We'll be in touch when general registration opens and further details of
the event become available, which shouldn't be too far away. All details
will be on http://orconf.org as they become available.
As always we're looking for sponsorship for this year's event. If you
think you'd like to have your company's name associated with it, please
email us at orconf(a)fossi-foundation.org
<mailto:firstname.lastname@example.org> and we'll get talking.
Whether or not you're intending on presenting, we're hoping to see
everyone again for another year of great presentations and, this time, a
few good English ales.
The ORConf team
Registration is now open for the fifty-seventh meeting, which will be an
evening workshop, providing a hands-on introduction to NetBSD on
OSHUG #57 — Getting started with NetBSD on embedded platforms
On the 20 April 2017, 17:30 - 20:00 at BCS London, 1st Floor, The
Davidson Building, 5 Southampton Street, London, WC2E 7HA.
— Workshop scope
You're hired at the latest startup as a hardware engineer and required
to build the firmware which will run on "The Greatest Next Generation
Appliance" (GNA). The GNA boots, prints a message and interacts with a
device (in this case an LED).
In this workshop we cover how a person with an interest and a focus on
hardware can make progress with the software side by using the NetBSD
operating system and the features it offers to save considerable time
* NetBSD supports a wide & diverse range of systems & CPU architectures.
* Support for cross compilation is offered by default and works out of
* There is a high level language interface to interact with the system
* File integrity verification support to detect tampering of binaries
and preventing execution is builtin.
* An instance of the kernel can be run as a user process on different
operating systems where rapid development can take place.
Things we will cover:
1. An introduction to cross-compilation with build.sh and constructing
an image to boot on your hardware.
2. Interacting with the system using Lua (which is embedded in the
kernel, avoiding having to write C or have knowledge of OS internals) to
e.g. access GPIO.
3. Preventing the execution of tampered or unauthorised binaries with
4. Using rump kernel for rapid development away from a potentially slow
** Note: Due to budgeting cuts, "The Greatest Next Generation Appliance"
has not yet been purchased, so, the workshop will target the development
of the firmware on a Raspberry Pi or BeagleBone Black.**
— Participant requirements
You will need to bring:
* Your own laptop (running Windows, Linux or Mac OS X);
* A Raspberry Pi or BeagleBone Black;
* An appropriate SD card for your board;
* USB card reader to write a new OS image onto said SD card;
* An ethernet cable to connect board to laptop and/or a USB UART/FTDI
adapter to access the board via the serial console.
— Hosted by
Sevan Janiyan is founder of Venture 37, which provides system
administration & consultancy services. As a fan of operating systems and
computers with different CPU architectures, in his spare time he
maintains builds of open source software on a variety of systems
featuring PowerPC, SPARC and armv7l CPUs. He hopes to own a NeXTcube &
OMRON LUNA-88K2 one day.
Note: Please aim to arrive by 17:15 as the workshop will start at 17:30
Job opportunity for freelance electrical engineer / PCB designer
It's The Flash Pac <http://www.itstheflashpack.com/>k are an award winning
photo experience agency, specialising in creating fun, interactive
photography based experiences at live events. We are known for our
innovative approach to briefs, our ability to create striking branded
content, and our expertise in delivering amplification of content pre,
during, and post event.
We are in need of a electrical engineer to spec and design a small PCB for
the Raspberry Pi 2, in effect a Raspberry Pi ‘HAT’. The applicant must be
able to show recent examples of PCBs designed through to fabrication in
Eagle CAD or similar for a commercial client, a thorough understanding of
the Raspberry Pi 2 B+ is of benefit.
We have a technical requirements document and have sourced some components
but consultation is required to fully scope the work, to check that our
desired specifications are fully feasible and the components are sufficient
to fulfil the requirements.
For those interested please email me at (neil(a)itstheflashpack.com) with CV
We are pleased to announce the 2017 NetFPGA Design Challenge!
NetFPGA platforms are used by the networked systems community for close to
a decade. The platforms enable researchers and instructors to build
high-speed, hardware-accelerated networking systems. The platforms can be
used by researchers to prototype advanced services for next-generation
networked systems. By using Field Programmable Gate Arrays (FPGAs),
new types of packet routing circuits to be implemented and detailed
measurements of network traffic to be obtained.
The NetFPGA 2017 contest is a design challenge. The design teams are to
produce a working implementation employing any HW and SW design methodology
and targeting the NetFPGA SUME platform. The deadline for submissions is April
13th, 2017. The winners will be announced at the NetFPGA Developers
20th - Friday, 21st April, 2017 Cambridge, UK).
Challenge: Lowest Latency Switch
Low latency devices are being increasingly used across a large number of
applications. Low latency solutions are few, and are rarely open source.
The goal of this challenge is to provide a usable, high performance, open
source alternative to use by universities and organizations who need the
flexibility of open source.
The systems will be evaluated using OSNT, an Open Source Network Tester.
Test benches will be available online, for users to experiment and
independently evaluate their design. The competition is open to students of
all levels (undergraduate and postgraduate), as well as to non students.
There is no need to own a NetFPGA SUME platform to take part in the
competition although, clearly, development and testing will be made easier
if you have access to this platform.
First place: 500GBP
Best students project: 500GBP
The winning projects and runner ups will be invited to present their work
at the NetFPGA Developers Summit 2017.
All challenge participants are keenly encouraged to attend the NetFPGA
Summit and are entitled to a reduced registration rate.
The design challenge prizes are generously supported by IMC
More details can be found at:
The NetFPGA Team