Hi All,
The theme for the meeting on the evening of Thursday 19th May will be chip/digital design/FPGA. We already have two talks confirmed and are looking for a third. Perhaps someone:
* could give a talk on MyHDL or one of the other gentler on-ramps? * has some experiences to share with respect to learning a HDL and/or using a FPGAs in projects? * has designed their own CPU from scratch, implemented in FPGA or discrete logic? * wrote a simulator for a classic CPU architecture?
Talk proposals and suggestions for speakers would be most helpful!
Cheers,
Andrew
Oh that sounds cool have you got someone covering Project IceStorm http://www.clifford.at/icestorm/ ?
On Wed, Mar 30, 2016 at 10:40 AM, Andrew Back arback@computer.org wrote:
Hi All,
The theme for the meeting on the evening of Thursday 19th May will be chip/digital design/FPGA. We already have two talks confirmed and are looking for a third. Perhaps someone:
- could give a talk on MyHDL or one of the other gentler on-ramps?
- has some experiences to share with respect to learning a HDL and/or
using a FPGAs in projects?
- has designed their own CPU from scratch, implemented in FPGA or
discrete logic?
- wrote a simulator for a classic CPU architecture?
Talk proposals and suggestions for speakers would be most helpful!
Cheers,
Andrew
oshug mailing list oshug@oshug.org http://oshug.org/cgi-bin/mailman/listinfo/oshug
On 30 March 2016 at 14:34, Alan Wood folknology@gmail.com wrote:
Oh that sounds cool have you got someone covering Project IceStorm http://www.clifford.at/icestorm/ ?
Nope. Have you got experience with it? :o)
On Wed, Mar 30, 2016 at 10:40 AM, Andrew Back arback@computer.org wrote:
Hi All,
The theme for the meeting on the evening of Thursday 19th May will be chip/digital design/FPGA. We already have two talks confirmed and are looking for a third. Perhaps someone:
- could give a talk on MyHDL or one of the other gentler on-ramps?
- has some experiences to share with respect to learning a HDL and/or
using a FPGAs in projects?
- has designed their own CPU from scratch, implemented in FPGA or
discrete logic?
- wrote a simulator for a classic CPU architecture?
Talk proposals and suggestions for speakers would be most helpful!
Cheers,
Andrew
oshug mailing list oshug@oshug.org http://oshug.org/cgi-bin/mailman/listinfo/oshug
-- regards Al
oshug mailing list oshug@oshug.org http://oshug.org/cgi-bin/mailman/listinfo/oshug
Yes, I have been using it lets have a chat as may well be ideal for the event theme..
On Wed, Mar 30, 2016 at 2:57 PM, Andrew Back arback@computer.org wrote:
On 30 March 2016 at 14:34, Alan Wood folknology@gmail.com wrote:
Oh that sounds cool have you got someone covering Project IceStorm http://www.clifford.at/icestorm/ ?
Nope. Have you got experience with it? :o)
On Wed, Mar 30, 2016 at 10:40 AM, Andrew Back arback@computer.org
wrote:
Hi All,
The theme for the meeting on the evening of Thursday 19th May will be chip/digital design/FPGA. We already have two talks confirmed and are looking for a third. Perhaps someone:
- could give a talk on MyHDL or one of the other gentler on-ramps?
- has some experiences to share with respect to learning a HDL and/or
using a FPGAs in projects?
- has designed their own CPU from scratch, implemented in FPGA or
discrete logic?
- wrote a simulator for a classic CPU architecture?
Talk proposals and suggestions for speakers would be most helpful!
Cheers,
Andrew
oshug mailing list oshug@oshug.org http://oshug.org/cgi-bin/mailman/listinfo/oshug
-- regards Al
oshug mailing list oshug@oshug.org http://oshug.org/cgi-bin/mailman/listinfo/oshug
-- Andrew Back FRSA MIEEE http://carrierdetect.com
oshug mailing list oshug@oshug.org http://oshug.org/cgi-bin/mailman/listinfo/oshug
-
Alan Wood -
Andrew Back