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Open Source Hardware Camp 2017 (2nd & 3rd Sept) Call for Participation.
by Andrew Back 04 Apr '17

04 Apr '17

Hello, This year Open Source Hardware Camp will take place over the weekend of Saturday 2nd & Sunday 3rd September, hosted as part of the Wuthering Bytes festival in Hebden Bridge, which in 2017 will take place over the course of 10 days (again!) We will be returning to the Birchcliffe Centre in Hebden Bridge, which benefits from the convenience of adjoining, budget accommodation. Proposals for talks and workshops for OSHCamp 2017 are invited! There is no theme and topics may include, for example: * Open source hardware projects * Open development practices and principles * Novel/interesting/fun projects built using open source hardware * Tools (hardware and software) * Skills and techniques, e.g. PCB fab, DIY SMT assembly * Relevant technologies, e.g. SPI/I2C bus programming * ...something else relevant to the community If you would like to give a talk on the Saturday and/or run a workshop on the Sunday please contact me off-list. **** Note that the deadline for submitting titles and abstracts is Monday 1st May. If you would like to discuss ideas etc. please get in touch sooner, rather than later. **** Other events running as part of Wuthering Bytes 2017 and which may be of interest: * Fri 1st: Wuthering Bytes Festival Day * Wed 6th & Thurs 7th: Chip Hack (http://chiphack.org/) * Thurs 7th PM & Fri 8th AM: EDSAC Challenge * Fri 8th AM - Sunday 10th PM: GNU ORConf (http://orconf.org/) Further details on these events to be provided in due course. Cheers, Andrew PS. If you are planning on coming along and thinking of staying at the adjoining hosted, it is worth noting that this can book up quickly. http://www.hebdenbridgehostel.co.uk/ PPS. Super Early Bird tickets for the super organised: https://www.eventbrite.co.uk/e/open-source-hardware-camp-2017-tickets-31845… (pretty sure Eventbrite don't take payment until after the event). -- Andrew Back http://abopen.com

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NetFPGA Developers Summit - Call For Participation
by Neelakandan 29 Mar '17

29 Mar '17

We welcome you to join us at the University of Cambridge on April 20-21, 2017 for the NetFPGA Developers Summit [1]. Held immediately prior to Eurosys 2017, this event is intended to permit participants attend both events with reduced intercontinental travel. The programme includes presentations, live demonstrations, and group discussions on topics that are of an interest to the NetFPGA community. This event will run "un-conference style" in that we brainstorm the actual session schedule on the first morning, with a focus on interactive topics that reflect the interests and exploit the knowledge of the attendees -- but there's also room for traditional talks, etc. There are plenty of break-out rooms for small groups to meet as they see fit. Confirmed topics include: * Running P4 programmes on NetFPGA * Low latency networking * Running network services in hardware * Optical networks * Traffic control tools * More -- See the draft programme on the Wiki [1] See you in Cambridge, The NetFPGA Team http://www.netfpga.org [1] NetFPGA-Developers-Summit-2017 <https://github.com/NetFPGA/NetFPGA-public/wiki/NetFPGA-Developers-Summit-20…>

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Fwd: ORConf 2017 call for participation
by Andrew Back 15 Mar '17

15 Mar '17

The ORCONF 2017 CFP is out! Why not head up to Hebden Bridge and make a week of it, with Open Source Hardware Camp, ORCONF and Chip Hack :o) Details below. Cheers, Andrew -------- Forwarded Message -------- Subject: [Orconf-announce] ORConf 2017 call for participation Date: Wed, 15 Mar 2017 23:03:14 +1100 From: Julius Baxter <julius(a)fossi-foundation.org> To: orconf-announce(a)lists.librecores.org Hi all, ORConf 2017 will be held in Hebden Bridge in the UK from Friday to Sunday, September 8th to the 10th. I'd like to announce that we've opened submissions for presentations, posters and hardware displays at the event. Proposals may be submitted through this form: https://goo.gl/forms/fwALSQvbyUfE83Fh1 ORConf aims to be an event aimed at anyone involved in free and open source computer system design, with an emphasis on open source digital design. So if you contribute to a tool to help put systems together, or develop on and debug them, or publish components and IP, or even make fully-open source chips(!) we'd very much like to hear from you! ORConf this year is being held as part of the esteemed Wuthering Bytes Festival of Technology: http://wutheringbytes.com/ There will be events in Hebden Bridge starting September 1st, so do check it out. We'll be in touch when general registration opens and further details of the event become available, which shouldn't be too far away. All details will be on http://orconf.org as they become available. As always we're looking for sponsorship for this year's event. If you think you'd like to have your company's name associated with it, please email us at orconf(a)fossi-foundation.org <mailto:orconf@fossi-foundation.org> and we'll get talking. Whether or not you're intending on presenting, we're hoping to see everyone again for another year of great presentations and, this time, a few good English ales. Cheers, The ORConf team

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OSHUG 57 — Getting started with NetBSD on embedded platforms, Thursday 20th April.
by Andrew Back 15 Mar '17

15 Mar '17

Hello, Registration is now open for the fifty-seventh meeting, which will be an evening workshop, providing a hands-on introduction to NetBSD on embedded platforms. Cheers, Andrew // OSHUG #57 — Getting started with NetBSD on embedded platforms On the 20 April 2017, 17:30 - 20:00 at BCS London, 1st Floor, The Davidson Building, 5 Southampton Street, London, WC2E 7HA. Registration: http://oshug.org/event/57 — Workshop scope You're hired at the latest startup as a hardware engineer and required to build the firmware which will run on "The Greatest Next Generation Appliance" (GNA). The GNA boots, prints a message and interacts with a device (in this case an LED). In this workshop we cover how a person with an interest and a focus on hardware can make progress with the software side by using the NetBSD operating system and the features it offers to save considerable time and effort. * NetBSD supports a wide & diverse range of systems & CPU architectures. * Support for cross compilation is offered by default and works out of the box. * There is a high level language interface to interact with the system internals. * File integrity verification support to detect tampering of binaries and preventing execution is builtin. * An instance of the kernel can be run as a user process on different operating systems where rapid development can take place. Things we will cover: 1. An introduction to cross-compilation with build.sh and constructing an image to boot on your hardware. 2. Interacting with the system using Lua (which is embedded in the kernel, avoiding having to write C or have knowledge of OS internals) to e.g. access GPIO. 3. Preventing the execution of tampered or unauthorised binaries with veriexec. 4. Using rump kernel for rapid development away from a potentially slow dev board. ** Note: Due to budgeting cuts, "The Greatest Next Generation Appliance" has not yet been purchased, so, the workshop will target the development of the firmware on a Raspberry Pi or BeagleBone Black.** — Participant requirements You will need to bring: * Your own laptop (running Windows, Linux or Mac OS X); * A Raspberry Pi or BeagleBone Black; * An appropriate SD card for your board; * USB card reader to write a new OS image onto said SD card; * An ethernet cable to connect board to laptop and/or a USB UART/FTDI adapter to access the board via the serial console. — Hosted by Sevan Janiyan is founder of Venture 37, which provides system administration & consultancy services. As a fan of operating systems and computers with different CPU architectures, in his spare time he maintains builds of open source software on a variety of systems featuring PowerPC, SPARC and armv7l CPUs. He hopes to own a NeXTcube & OMRON LUNA-88K2 one day. Note: Please aim to arrive by 17:15 as the workshop will start at 17:30 prompt. -- Andrew Back http://abopen.com

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Looking for freelance PCB designer
by Neil Thomson 09 Mar '17

09 Mar '17

Job opportunity for freelance electrical engineer / PCB designer It's The Flash Pac <http://www.itstheflashpack.com/>k are an award winning photo experience agency, specialising in creating fun, interactive photography based experiences at live events. We are known for our innovative approach to briefs, our ability to create striking branded content, and our expertise in delivering amplification of content pre, during, and post event. We are in need of a electrical engineer to spec and design a small PCB for the Raspberry Pi 2, in effect a Raspberry Pi ‘HAT’. The applicant must be able to show recent examples of PCBs designed through to fabrication in Eagle CAD or similar for a commercial client, a thorough understanding of the Raspberry Pi 2 B+ is of benefit. We have a technical requirements document and have sourced some components but consultation is required to fully scope the work, to check that our desired specifications are fully feasible and the components are sufficient to fulfil the requirements. For those interested please email me at (neil(a)itstheflashpack.com) with CV / portfolio. Thanks!

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NetFPGA Design Challenge - Call For Participation
by Neelakandan 04 Mar '17

04 Mar '17

We are pleased to announce the 2017 NetFPGA Design Challenge! NetFPGA platforms are used by the networked systems community for close to a decade. The platforms enable researchers and instructors to build high-speed, hardware-accelerated networking systems. The platforms can be used by researchers to prototype advanced services for next-generation networked systems. By using Field Programmable Gate Arrays (FPGAs), NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. The NetFPGA 2017 contest is a design challenge. The design teams are to produce a working implementation employing any HW and SW design methodology and targeting the NetFPGA SUME platform. The deadline for submissions is April 13th, 2017. The winners will be announced at the NetFPGA Developers Summit (Thursday 20th - Friday, 21st April, 2017 Cambridge, UK). Challenge: Lowest Latency Switch Low latency devices are being increasingly used across a large number of applications. Low latency solutions are few, and are rarely open source. The goal of this challenge is to provide a usable, high performance, open source alternative to use by universities and organizations who need the flexibility of open source. The systems will be evaluated using OSNT, an Open Source Network Tester. Test benches will be available online, for users to experiment and independently evaluate their design. The competition is open to students of all levels (undergraduate and postgraduate), as well as to non students. There is no need to own a NetFPGA SUME platform to take part in the competition although, clearly, development and testing will be made easier if you have access to this platform. Team Prizes: First place: 500GBP Best students project: 500GBP The winning projects and runner ups will be invited to present their work at the NetFPGA Developers Summit 2017. All challenge participants are keenly encouraged to attend the NetFPGA Developers Summit and are entitled to a reduced registration rate. The design challenge prizes are generously supported by IMC http://www.imc.nl/ More details can be found at: http://www.cl.cam.ac.uk/research/srg/netfpga/challenge2017 Good luck! The NetFPGA Team http://www.netfpga.org

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Cirrus Logic Voyager CL-PS7000 documentation
by Sevan / Venture37 13 Feb '17

13 Feb '17

Hello, There is a software emulator for the Apple Newton PDA called Einstein, the developers are looking for documentation for a legacy chipset manufactured by Cirrus Logic to improve the emulator. Would any of you happen to have a copy of the Cirrus Logic Voyager CL-PS7000 Apple Newton PCA Chip Set Engineering Specification? http://www.warthman.com/projects-cirrus-logic-voyager-architectural-overvie… https://twitter.com/stevenf/status/831176567627804672 Apologies for the talk of legacy closed hardware but it is about open source software if that makes it any better :) https://github.com/pguyot/Einstein Sevan

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OSHUG 56 — An introduction to software-defined radio with LimeSDR (workshop), Fri 24th March.
by Andrew Back 12 Feb '17

12 Feb '17

Hello, Registration is now open for the fifty-sixth meeting, which will be a one day workshop, providing a hands-on introduction to software-defined radio with the LimeSDR. This will cover key concepts and LMS7002M FPRF IC architecture, and include simple digital radio examples along with a demonstrations of advanced systems, such as 4G femtocell. // OSHUG #56 — An introduction to software-defined radio with LimeSDR On the 24 March 2017, 09:00 - 17:00 at BCS London, 1st Floor, The Davidson Building, 5 Southampton Street, London, WC2E 7HA. Registration: https://events.bcs.org/book/2451/ A Software-Defined Radio (SDR) is a highly reconfigurable radio that can be used for many different radio applications through simply changing the software that links with it. An example of such a reconfigurable radio is the LimeSDR, which can both transmit and receive data and voice, using just about any wireless system. The LimeSDR was launched by Lime Microsystems in May 2016 via a crowdfunding campaign, and is now shipping to over 3,500 customers worldwide. It is based on the Lime Microsystems LMS7002M Field Programmable RF (FPRF) 2x2 MIMO transceiver, which continuously covers frequencies from 100kHz to 3.8GHz. The LMS7002M has been successfully used in a wide range of digital radio applications, including 2G/4G Femtocell base stations, GNSS, DAB, DVBT receivers and RF test and measurement equipment. The LimeSDR also includes an FPGA and USB 3.0 to provide host connectivity. — Workshop scope The heart of the day is to provide a practical ‘hands-on’ afternoon session using the LimeSDR with the Lime Suite GUI and FFT Viewer. Then to use GNU Octave and Pothos to make some very simple digital radio examples. To facilitate this, the morning will include introductory talks explaining the purpose of the various analogue and digital blocks included in the LMS7002M. It will also include tutorial material covering the key concepts required to understand modern digital radio transceivers, and how to use them, as well as practical issues associated with radio reception. In addition the day will feature some advanced demonstrations showing the full capabilities of the LimeSDR and its LMS7002M transceiver, including 4G Femtocell, as well as educational examples such as a simple OFDM transceiver data link. — Participant requirements ** Participants are required to bring a laptop computer with USB 3.0 ** Minimum computer hardware requirements are USB 3.0 capability and 2GB RAM. Although no prior knowledge of radio is required, an awareness of basic terminology will be very helpful. Basic computer programming and administration skills will also be helpful. The software that will be used must be installed prior to the event. For details see: https://wiki.myriadrf.org/LimeSDR_Workshop — What is provided * LimeSDR hardware will be provided for use during the workshop * A light lunch will be provided and please ensure that any dietary requirements are made clear during registration — Hosted by The workshop will be led by Dr. Danny Webster, who has over 25 years of experience in the field of RF design covering varied applications from military radio to cellular infrastructure. Danny Graduated from Swansea University in 1988 and was awarded a PhD from University College London in 1995. From 1995 he worked as a Research Fellow at University College London and was a consultant to companies such as Nokia, Roke Manor Research and Agilent in Santa Rosa. From 2001 he was with Hipertech and joined Lime Micro in 2005 as Principle Design Engineer (RF) working on Field programmable RF ICs. Danny is a senior member of the IEEE. This workshop is free to attend and hosted by Lime Microsystems in partnership with the BCS Open Source Specialist Group and the Open Source Hardware User Group. Note: Please aim to arrive by 08:45 as the workshop will start at 09:00 prompt. -- Andrew Back http://abopen.com

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OSHUG 55 — FPGA projects past, planned and possible, Thursday 16th February.
by Andrew Back 05 Feb '17

05 Feb '17

Hello, Registration is now open for the February meeting, details of which can be found below. We also still have space for 1 or 2 more short talks of 10-15 minutes, so if you have an idea for a talk, get in touch! Cheers, Andrew // Event #55 — FPGA projects past, planned and possible On the 16 February 2017, 18:00 - 20:00 at BCS London, 1st Floor, The Davidson Building, 5 Southampton Street, London, WC2E 7HA. Registration: http://oshug.org/event/55 The fifty-fifth meeting will feature a series of shorter talks that explore past, planned and possible projects which use FPGAs. — FPGA Projects - What would I build and why would I want to PLAs have been interesting ever since the 70s when digital logic often became complex, consuming unnecessary space and power. Back then the cost of PLA deployment was high and it has continued to be high until recently. Now that we have powerful, low cost development platforms and relatively cheap FPGAs the cost equation has shifted radically. * Paul Tanner is a consultant, developer and maker in wood, metal, plastic, electronics and software. His day job is IT-based business improvement for SMEs. By night he turns energy nut, creating tools to optimise energy use. Paul graduated in electronics and was responsible for hardware and software product development and customer services in several product and service start-ups, switching to consulting in 2000. — Using FPGAs to solve realtime problems Microcontrollers a great platform to solve basic control problems in electronics, with simple motor drivers and sensors readily avaiable and easy to integrate. However, when the motor control becomes more complex with BLDC and FOC things get much more tricky. When you have to use multiple BLDC motors and more complex sensors with image processing the poor microcontroller quickly becomes to swamped to provide control in realtime. This is where adding FPGA technology makes a great deal of sense particularly in mutli-discipline projects like robotics where many sensors, motors and image processing will need to be managed and controlled concurrently. A robotics platform must therefore contain both concurrent hardware resources, algorithmic control through soft or hard cores along with communication protocols. * Alan Wood has been working with parallel distributed programming for several decades. His recent work includes smart grids, 3D printers, robotics, automation and biotec diagnostics. His current research is focused on machine learning, inference and image processing for embedded applications using FPGA and multi-cores. He is a long term advocate and moderator (aka Folknology) for xCORE and other opensource communities, as well as a founder of Surrey and Hampshire Makerspace and myStorm FPGA development boards. — FPGAs in the Cloud? It is no secret that FPGA based computing machines are great at dealing with certain types of workloads that conventional CPU based machines can not efficiently handle. These machines, alongside their GPU and even custom ASIC based brethren, have been filling up racks in large data centres all over the globe helping speed up systems that have components of machine learning, complex analytics and even video processing. This short talk will have a look at the state of FPGAs in the datacenter and discuss the recent developments around the availability of FPGA equipped computing nodes in commodity cloud providers. * Omer Kilic is an Embedded Systems Engineer who enjoys working with small connected computers of all shapes and sizes. He works at the various intersections of hardware and software engineering practices, product development and manufacturing. — Chip Hack 2017 & EDSAC Challenge This talk will introduce and issue a call for participation for two events that are being hosted as part of the Wuthering Bytes technology festival, that will take place in Hebden Bridge in September, in the week following Open Source Hardware Camp 2017. Chip Hack is a two day hands-on workshop that provides a gentle introduction to programming FPGAs and is aimed at novices with no prior experience of Hardware Description Languages (HDLs) or FPGAs. This will be followed immediately by a challenge event, during which a small team of experts will work to extend a basic functional FPGA model of EDSAC — the pioneering computer designed and constructed at Cambridge University, and which was operational by 1949. * Dr Jeremy Bennett is founder and Chief Executive of Embecosm, a consultancy implementing open source compilers and chip simulators for major corporations around the world. He is a author of the standard textbook "Introduction to Compiling Techniques" (McGraw-Hill 1990, 1995, 2003). Contact him at: jeremy.bennett(a)embecosm.com. Note: Please aim to arrive by 18:15 as the event will start at 18:30 prompt. // -- Andrew Back http://abopen.com

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Fwd: 2017 NetFPGA open source design challenge
by Alex Bradbury 01 Feb '17

01 Feb '17

The NetFPGA project are running an open source design challenge, that might be of interest to some people on this list. For more info, see http://www.cl.cam.ac.uk/research/srg/netfpga/challenge2017/ Best, Alex ---------- Forwarded message ---------- We are pleased to announce the 2017 NetFPGA Design Challenge! NetFPGA platforms are used by the networked systems community for close to a decade. The platforms enable researchers and instructors to build high-speed, hardware-accelerated networking systems. The platforms can be used by researchers to prototype advanced services for next-generation networked systems. By using Field Programmable Gate Arrays (FPGAs), NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. The NetFPGA 2017 contest is a design challenge. The design teams are to produce a working implementation employing any HW and SW design methodology and targeting the NetFPGA SUME platform. The deadline for submissions is April 13th, 2017. The winners will be announced at the NetFPGA Developers Summit (Thursday 20th - Friday, 21st April, 2017 Cambridge, UK). Challenge: Lowest Latency Switch Low latency devices are being increasingly used across a large number of applications. Low latency solutions are few, and are rarely open source. The goal of this challenge is to provide a usable, high performance, open source alternative to use by universities and organizations who need the flexibility of open source. The systems will be evaluated using OSNT, an Open Source Network Tester. Test benches will be available online, for users to experiment and independently evaluate their design. The competition is open to students of all levels (undergraduate and postgraduate), as well as to non students. There is no need to own a NetFPGA SUME platform to take part in the competition although, clearly, development and testing will be made easier if you have access to this platform. Team Prizes: First place: £500 Best students project: £500 The winning projects and runner ups will be invited to present their work at the NetFPGA Developers Summit 2017. All challenge participants are keenly encouraged to attend the NetFPGA Developers Summit and are entitled to a reduced registration rate. The design challenge prizes are generously supported by IMC http://www.imc.nl/ More details can be found at: http://www.cl.cam.ac.uk/research/srg/netfpga/challenge2017 Good luck! The NetFPGA Team http://www.netfpga.org

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