All,

I would like to present on the topic "Cocotb" at a future OSHUG event.

Cocotb[1] is an open-source Python framework for verifying RTL written in [System]Verilog or VHDL.  It has been used to successfully verify multiple large FPGA designs (>500k registers).  It also serves to bridge the gap between traditional FPGA/ASIC practices and software developers, as well as helping to introduce agile methodology and continuous integration to hardware teams.

Cocotb works well with Icarus Verilog, providing a powerful open-source alternative to SystemVerilog based verification frameworks like UVM which require users to spend many thousands of pounds on simulator licenses.  For those wishing to use SystemVerilog without paying for a license it can also be used with the free version of Mentor Modelsim (Altera Starter Edition).

A presentation would be a good follow-up to the up-coming ChipHack event to demonstrate one of the possible ways of verifying more complex designs for those wishing to pursue FPGA development further.  Depending on the experience and interests of the audience I can present different aspects of Cocotb, e.g. how the framework was designed, co-simulating unmodified software, interacting with the outside world from simulation, SoC driver development, lessons learned etc.

Thanks,

Chris

[1] http://potentialventures.github.io/cocotb/