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NetFPGA Design Challenge - Call For Participation
by Neelakandan 04 Mar '17

04 Mar '17

We are pleased to announce the 2017 NetFPGA Design Challenge! NetFPGA platforms are used by the networked systems community for close to a decade. The platforms enable researchers and instructors to build high-speed, hardware-accelerated networking systems. The platforms can be used by researchers to prototype advanced services for next-generation networked systems. By using Field Programmable Gate Arrays (FPGAs), NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. The NetFPGA 2017 contest is a design challenge. The design teams are to produce a working implementation employing any HW and SW design methodology and targeting the NetFPGA SUME platform. The deadline for submissions is April 13th, 2017. The winners will be announced at the NetFPGA Developers Summit (Thursday 20th - Friday, 21st April, 2017 Cambridge, UK). Challenge: Lowest Latency Switch Low latency devices are being increasingly used across a large number of applications. Low latency solutions are few, and are rarely open source. The goal of this challenge is to provide a usable, high performance, open source alternative to use by universities and organizations who need the flexibility of open source. The systems will be evaluated using OSNT, an Open Source Network Tester. Test benches will be available online, for users to experiment and independently evaluate their design. The competition is open to students of all levels (undergraduate and postgraduate), as well as to non students. There is no need to own a NetFPGA SUME platform to take part in the competition although, clearly, development and testing will be made easier if you have access to this platform. Team Prizes: First place: 500GBP Best students project: 500GBP The winning projects and runner ups will be invited to present their work at the NetFPGA Developers Summit 2017. All challenge participants are keenly encouraged to attend the NetFPGA Developers Summit and are entitled to a reduced registration rate. The design challenge prizes are generously supported by IMC http://www.imc.nl/ More details can be found at: http://www.cl.cam.ac.uk/research/srg/netfpga/challenge2017 Good luck! The NetFPGA Team http://www.netfpga.org

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Cirrus Logic Voyager CL-PS7000 documentation
by Sevan / Venture37 13 Feb '17

13 Feb '17

Hello, There is a software emulator for the Apple Newton PDA called Einstein, the developers are looking for documentation for a legacy chipset manufactured by Cirrus Logic to improve the emulator. Would any of you happen to have a copy of the Cirrus Logic Voyager CL-PS7000 Apple Newton PCA Chip Set Engineering Specification? http://www.warthman.com/projects-cirrus-logic-voyager-architectural-overvie… https://twitter.com/stevenf/status/831176567627804672 Apologies for the talk of legacy closed hardware but it is about open source software if that makes it any better :) https://github.com/pguyot/Einstein Sevan

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OSHUG 56 — An introduction to software-defined radio with LimeSDR (workshop), Fri 24th March.
by Andrew Back 12 Feb '17

12 Feb '17

Hello, Registration is now open for the fifty-sixth meeting, which will be a one day workshop, providing a hands-on introduction to software-defined radio with the LimeSDR. This will cover key concepts and LMS7002M FPRF IC architecture, and include simple digital radio examples along with a demonstrations of advanced systems, such as 4G femtocell. // OSHUG #56 — An introduction to software-defined radio with LimeSDR On the 24 March 2017, 09:00 - 17:00 at BCS London, 1st Floor, The Davidson Building, 5 Southampton Street, London, WC2E 7HA. Registration: https://events.bcs.org/book/2451/ A Software-Defined Radio (SDR) is a highly reconfigurable radio that can be used for many different radio applications through simply changing the software that links with it. An example of such a reconfigurable radio is the LimeSDR, which can both transmit and receive data and voice, using just about any wireless system. The LimeSDR was launched by Lime Microsystems in May 2016 via a crowdfunding campaign, and is now shipping to over 3,500 customers worldwide. It is based on the Lime Microsystems LMS7002M Field Programmable RF (FPRF) 2x2 MIMO transceiver, which continuously covers frequencies from 100kHz to 3.8GHz. The LMS7002M has been successfully used in a wide range of digital radio applications, including 2G/4G Femtocell base stations, GNSS, DAB, DVBT receivers and RF test and measurement equipment. The LimeSDR also includes an FPGA and USB 3.0 to provide host connectivity. — Workshop scope The heart of the day is to provide a practical ‘hands-on’ afternoon session using the LimeSDR with the Lime Suite GUI and FFT Viewer. Then to use GNU Octave and Pothos to make some very simple digital radio examples. To facilitate this, the morning will include introductory talks explaining the purpose of the various analogue and digital blocks included in the LMS7002M. It will also include tutorial material covering the key concepts required to understand modern digital radio transceivers, and how to use them, as well as practical issues associated with radio reception. In addition the day will feature some advanced demonstrations showing the full capabilities of the LimeSDR and its LMS7002M transceiver, including 4G Femtocell, as well as educational examples such as a simple OFDM transceiver data link. — Participant requirements ** Participants are required to bring a laptop computer with USB 3.0 ** Minimum computer hardware requirements are USB 3.0 capability and 2GB RAM. Although no prior knowledge of radio is required, an awareness of basic terminology will be very helpful. Basic computer programming and administration skills will also be helpful. The software that will be used must be installed prior to the event. For details see: https://wiki.myriadrf.org/LimeSDR_Workshop — What is provided * LimeSDR hardware will be provided for use during the workshop * A light lunch will be provided and please ensure that any dietary requirements are made clear during registration — Hosted by The workshop will be led by Dr. Danny Webster, who has over 25 years of experience in the field of RF design covering varied applications from military radio to cellular infrastructure. Danny Graduated from Swansea University in 1988 and was awarded a PhD from University College London in 1995. From 1995 he worked as a Research Fellow at University College London and was a consultant to companies such as Nokia, Roke Manor Research and Agilent in Santa Rosa. From 2001 he was with Hipertech and joined Lime Micro in 2005 as Principle Design Engineer (RF) working on Field programmable RF ICs. Danny is a senior member of the IEEE. This workshop is free to attend and hosted by Lime Microsystems in partnership with the BCS Open Source Specialist Group and the Open Source Hardware User Group. Note: Please aim to arrive by 08:45 as the workshop will start at 09:00 prompt. -- Andrew Back http://abopen.com

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OSHUG 55 — FPGA projects past, planned and possible, Thursday 16th February.
by Andrew Back 05 Feb '17

05 Feb '17

Hello, Registration is now open for the February meeting, details of which can be found below. We also still have space for 1 or 2 more short talks of 10-15 minutes, so if you have an idea for a talk, get in touch! Cheers, Andrew // Event #55 — FPGA projects past, planned and possible On the 16 February 2017, 18:00 - 20:00 at BCS London, 1st Floor, The Davidson Building, 5 Southampton Street, London, WC2E 7HA. Registration: http://oshug.org/event/55 The fifty-fifth meeting will feature a series of shorter talks that explore past, planned and possible projects which use FPGAs. — FPGA Projects - What would I build and why would I want to PLAs have been interesting ever since the 70s when digital logic often became complex, consuming unnecessary space and power. Back then the cost of PLA deployment was high and it has continued to be high until recently. Now that we have powerful, low cost development platforms and relatively cheap FPGAs the cost equation has shifted radically. * Paul Tanner is a consultant, developer and maker in wood, metal, plastic, electronics and software. His day job is IT-based business improvement for SMEs. By night he turns energy nut, creating tools to optimise energy use. Paul graduated in electronics and was responsible for hardware and software product development and customer services in several product and service start-ups, switching to consulting in 2000. — Using FPGAs to solve realtime problems Microcontrollers a great platform to solve basic control problems in electronics, with simple motor drivers and sensors readily avaiable and easy to integrate. However, when the motor control becomes more complex with BLDC and FOC things get much more tricky. When you have to use multiple BLDC motors and more complex sensors with image processing the poor microcontroller quickly becomes to swamped to provide control in realtime. This is where adding FPGA technology makes a great deal of sense particularly in mutli-discipline projects like robotics where many sensors, motors and image processing will need to be managed and controlled concurrently. A robotics platform must therefore contain both concurrent hardware resources, algorithmic control through soft or hard cores along with communication protocols. * Alan Wood has been working with parallel distributed programming for several decades. His recent work includes smart grids, 3D printers, robotics, automation and biotec diagnostics. His current research is focused on machine learning, inference and image processing for embedded applications using FPGA and multi-cores. He is a long term advocate and moderator (aka Folknology) for xCORE and other opensource communities, as well as a founder of Surrey and Hampshire Makerspace and myStorm FPGA development boards. — FPGAs in the Cloud? It is no secret that FPGA based computing machines are great at dealing with certain types of workloads that conventional CPU based machines can not efficiently handle. These machines, alongside their GPU and even custom ASIC based brethren, have been filling up racks in large data centres all over the globe helping speed up systems that have components of machine learning, complex analytics and even video processing. This short talk will have a look at the state of FPGAs in the datacenter and discuss the recent developments around the availability of FPGA equipped computing nodes in commodity cloud providers. * Omer Kilic is an Embedded Systems Engineer who enjoys working with small connected computers of all shapes and sizes. He works at the various intersections of hardware and software engineering practices, product development and manufacturing. — Chip Hack 2017 & EDSAC Challenge This talk will introduce and issue a call for participation for two events that are being hosted as part of the Wuthering Bytes technology festival, that will take place in Hebden Bridge in September, in the week following Open Source Hardware Camp 2017. Chip Hack is a two day hands-on workshop that provides a gentle introduction to programming FPGAs and is aimed at novices with no prior experience of Hardware Description Languages (HDLs) or FPGAs. This will be followed immediately by a challenge event, during which a small team of experts will work to extend a basic functional FPGA model of EDSAC — the pioneering computer designed and constructed at Cambridge University, and which was operational by 1949. * Dr Jeremy Bennett is founder and Chief Executive of Embecosm, a consultancy implementing open source compilers and chip simulators for major corporations around the world. He is a author of the standard textbook "Introduction to Compiling Techniques" (McGraw-Hill 1990, 1995, 2003). Contact him at: jeremy.bennett(a)embecosm.com. Note: Please aim to arrive by 18:15 as the event will start at 18:30 prompt. // -- Andrew Back http://abopen.com

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Fwd: 2017 NetFPGA open source design challenge
by Alex Bradbury 01 Feb '17

01 Feb '17

The NetFPGA project are running an open source design challenge, that might be of interest to some people on this list. For more info, see http://www.cl.cam.ac.uk/research/srg/netfpga/challenge2017/ Best, Alex ---------- Forwarded message ---------- We are pleased to announce the 2017 NetFPGA Design Challenge! NetFPGA platforms are used by the networked systems community for close to a decade. The platforms enable researchers and instructors to build high-speed, hardware-accelerated networking systems. The platforms can be used by researchers to prototype advanced services for next-generation networked systems. By using Field Programmable Gate Arrays (FPGAs), NetFPGA enables new types of packet routing circuits to be implemented and detailed measurements of network traffic to be obtained. The NetFPGA 2017 contest is a design challenge. The design teams are to produce a working implementation employing any HW and SW design methodology and targeting the NetFPGA SUME platform. The deadline for submissions is April 13th, 2017. The winners will be announced at the NetFPGA Developers Summit (Thursday 20th - Friday, 21st April, 2017 Cambridge, UK). Challenge: Lowest Latency Switch Low latency devices are being increasingly used across a large number of applications. Low latency solutions are few, and are rarely open source. The goal of this challenge is to provide a usable, high performance, open source alternative to use by universities and organizations who need the flexibility of open source. The systems will be evaluated using OSNT, an Open Source Network Tester. Test benches will be available online, for users to experiment and independently evaluate their design. The competition is open to students of all levels (undergraduate and postgraduate), as well as to non students. There is no need to own a NetFPGA SUME platform to take part in the competition although, clearly, development and testing will be made easier if you have access to this platform. Team Prizes: First place: £500 Best students project: £500 The winning projects and runner ups will be invited to present their work at the NetFPGA Developers Summit 2017. All challenge participants are keenly encouraged to attend the NetFPGA Developers Summit and are entitled to a reduced registration rate. The design challenge prizes are generously supported by IMC http://www.imc.nl/ More details can be found at: http://www.cl.cam.ac.uk/research/srg/netfpga/challenge2017 Good luck! The NetFPGA Team http://www.netfpga.org

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Personal Privacy Online (The Dark Web, Investigatory Powers Act), Thursday 19th January.
by Andrew Back 12 Jan '17

12 Jan '17

Hi All, There are no hardware talks this month, but there will be an excellent series of 3 talks hosted by the BCS OSSG next Thursday, on theme of personal online privacy. Details below. Best, Andrew // Personal Privacy Online (The Dark Web, Investigatory Powers Act) On the 19 January 2017, 18:00 - 20:00 at BCS London, 1st Floor, The Davidson Building, 5 Southampton Street, London, WC2E 7HA. Registration: https://events.bcs.org/book/2408/ We explore the theme of personal rights and privacy on the modern Internet, with a talk on The Dark Web, covering insights on one of the larger anonymous marketplaces online and another on the new Investigatory Powers Act. — The Investigatory Powers Act: What is it? The Investigatory Powers Act also known as the Snoopers Charter is now law, find out what that means for you and your company. The Snoopers Charter would require metadata on every email, website visit and social media log to be recorded. It covers hacking and mass hacking performed by Government agencies. Its powers can be enforced across the world. It contains over 270 clauses and dwarfs the computer misuse act in terms of size, so this is going to be a speed run covering some of the high points. * Glyn Wintle is a security evangelist and software engineer. He has given evidence in Parliament, frequently gives technical talks about security and is well know for his work with the Open Rights Group. — The Dark Web Within the last years, governmental bodies have been futilely trying to fight against dark web hosted marketplaces. Shortly after the closing of “The Silk Road” by the FBI and Europol in 2013, new successors have been established. Through the combination of cryptocurrencies and nonstandard communication protocols and tools, agents can anonymously trade in a marketplace for illegal items without leaving any record. This talk will presents a research carried out to gain insights on the products and services sold within one of the larger marketplaces for drugs, fake ids and weapons on the Internet, Agora, and on new developments after the demise of Agora. The team behind the research included Andres Baravalle, Sin Wee Lee, Germans Zaharovs (research intern) and Mauro Lopez Sanchez (final year project). The work has been featured on the front page on The Times and on the Guardian, amongst other media. * Andres Baravalle works in the in the University of East London as Senior Lecturer in Computing. He has been working in academia since 2004 (University of Turin, University of Sheffield, Open University, University of East London), while also working as a contractor in industry. Andres has been developing in LAMP environments since 1999 and managing development teams since shortly after. In the past years he has been combining his expertise in web technologies with an interest on security and data science. “ He once made a student cry - by praising his work. Note: Please aim to arrive by 18:15 as the event will start at 18:30 prompt. -- Andrew Back http://abopen.com

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February meeting theme/talks?
by Andrew Back 11 Jan '17

11 Jan '17

Hello, Following the last meeting — and probably in the pub ... — I seem to recall a theme and/or talks being suggested for the meeting on the evening of Thursday 16th February. Does this sound familiar to anyone? Failing which, new suggestions welcome :o) Cheers, Andrew -- Andrew Back http://abopen.com

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Residencies in Shenzhen for UK makers
by marc barto 03 Jan '17

03 Jan '17

Happy new year all This call for makers might interest some OSHUG members: It a residency programme for UK makers to go to Shenzhen (arguably the electronics manufacturing capital of the world). All info here: http://creativeconomy.britishcouncil.org/blog/16/12/16 /calling-all-uk-makers-opportunity-travel-shenzhen/ One of the residency is with Makeblock to prototype a kit with their team. I have visited their office in Shenzhen, it's pretty much a mini-Legoland for hardware makers. Other residencies are around maker education, sustainability, 3D Printing etc. And generally this city is worth a trip to source components or discover how the Shanzhai <http://www.vam.ac.uk/shekou/from-shenzhen-shanzhai-and-the-maker-movement/> ecosystem works, that said don't go there if you can't stand air pollution! cheers -- Marc @marc_in_london <https://twitter.com/marc_in_london>

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OSHUG #53 — Getting started with FPGAs & Verilog using IceStorm & myStorm (workshop), Thursday 1st December.
by Andrew Back 30 Nov '16

30 Nov '16

Hello, Excited to announce that in a little over a month we will be jointly hosting with BCS OSSG, a 1-day workshop that will serve as an introduction to FPGAs and Verilog, via the most excellent project IceStorm/Yosys/Arachne-pnr open source toolchain and myStorm iCE40 FPGA board. You can find details below and note that at the time of writing there is a mistake on the BCS event page and the timing is 09:00-17:00, as on the OSHUG page. Place are limited, FPGA workshops have proven highly popular in the past and so if you would like to take part, I'd suggest registering sooner rather than later. However, please only register if you are confident that you can make it, as the workshop will likely sell out fairly quickly and we'd prefer to avoid having a waiting list and then empty seats on the day. Note that the venue for this is the RSA and not the BCS. There will also be a regular meeting in the evening, but at a different venue and further details will be provided in due course. Cheers, Andrew // On the 1 December 2016, 09:00 - 17:00 at Prince Philip Room, The Royal Society of Arts, 8 John Adam Street, London, WC2N 6EZ. Registration: http://oshug.org/event/53 A full day, hands-on FPGA programming workshop that is free to attend. The regular monthly meeting will then follow in the evening, but at a different venue and for details see the OSHUG No. 54 event page (to be added soon!). Please note that if you intend to attend both the workshop and evening meeting, you must register separately for each of these! — Workshop details In this workshop we will build some basic Verilog blocks and modules targeting low power, low cost FPGAs from the Lattice iCE40 series. The workshop will operate using a complete open source Verilog toolchain based around Yosys and Arachne-PNR, which can be run on Linux and OS X. We will cover basic sequential and combinational logic blocks. In addition we will show you how you can combine simple ARM microcontroller code running alongside and communicating with Verilog peripherals synthesised on a Lattice iCE40 FPGA, all running together on myStorm. This workshop will give participants a real taste of FPGA development in an open source software environment, using open source hardware. * Ken Boak started his professional career at BBC Research Department in 1986 working on digital signal processing systems for HDTV and subsequently over 30 years, a mix of 10 other technology companies, both UK and US based, in the fields of instrumentation, automation, telemetry telecomms. Ken has been interested in energy monitoring since the early 1990s, when he constructed a 4 seater electric car, and provided rudimentary energy analysis of the battery charge and discharge cycles. In 1998 he joined a South London company and designed a low power wireless, monitor device for automatic, remote gas and electricity meter reading. In 2009 Ken worked on the Onzo Energy Monitoring Kit, a commercial device that was ultimately distributed to Southern Electric customers. Then in 2010 he produced a series of educational devices to teach engineering undergraduates the principles of photovoltaic energy systems. Ken has continued his interests in energy monitoring, working collaboratively with Megni on the OpenEnergyMonitor project, the open Inverter Project and also for All Power Labs in Berkeley, California, where he was involved in power monitoring of wood gasifier generator sets. He tries to live a low impact lifestyle in a modest Edwardian house in Surrey, with a little help from modern electronics. * Alan Wood has been working with parallel distributed programming for several decades. His recent work includes smart grids, 3D printers, robotics, automation and biotec diagnostics. His current research is focused on machine learning for embedded applications using Motes on FPGA and emerging Asics. He is a long term advocate and moderator (aka Folknology) for xCORE and other opensource communities, as well as a founder of Surrey and Hampshire Makerspace. — What to bring Participants must bring a laptop computer and ideally one that is running either Linux or OS X. If your laptop is running Windows, you should also bring along a Raspberry Pi or similar Linux SBC, that you can use to build the toolchain and program myStorm over USB. Note: Please aim to arrive by 08:45 as the workshop will start at 09:00 prompt.

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Another RISC-V project
by Jeremy Bennett 29 Nov '16

29 Nov '16

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hot on the heels OnChip and Open-V of comes https://www.crowdsupply.com/sifive/hifive1 I note they have already met their target on the first day (it wasn't a very hard target). Jeremy - -- Tel: +44 (1590) 610184 Cell: +44 (7970) 676050 SkypeID: jeremybennett Twitter: @jeremypbennett Email: jeremy.bennett(a)embecosm.com Web: www.embecosm.com PGP key: 1024D/BEF58172FB4754E1 2009-03-20 -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iEYEARECAAYFAlg9qmQACgkQvvWBcvtHVOFH5QCfYP3W6aBQOYoHVH70YLhqiAhG q4kAn3JesS6OfLDaHMg30DJuU6+xR34e =yaiL -----END PGP SIGNATURE-----

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